Inter-IC Bus

Inter -IC bus is a synchronous bus that also operates on a master-slave principle. It is usually used for short distance communication between controllers and peripherals.
The protocols can support multiple masters as well as slaves. However, there has to be at least one master in the system. It uses two single-ended wires: SCL (Serial Clock Line) and SDA (Serial Data Line) for half-duplex communication. The protocol specification has 3 speed modes:

Standard mode: This mode allows transmission speeds up to 100kbps.

Fast mode: This mode extends the speed to 400kpbs

Fast mode plus: This mode supports speeds up to 1Mbps

High speed mode: In this mode speeds of up to 3.4Mbps are allowed.

Ultra-fast mode:There is also a 5 Mbps speed.

In a system connected by I2C protocol, there has to be at least one master. This master controls the system. I2C is an easily extensible protocol. It has no upper limit for number of devices that can be connected as long as the bus capacitance of 400pF is not exceeded. (Bus capacitance arises as a result of conductors being close to each other with a dielectric separating them. This capacitance is not intended but it exists.) The I2C bus supports both 7-bit and 10-bit addresses.

In 7-bit address, the highest 4-bits are hard-coded by the manufacturer of the device. The rest are programmed by the board designer. The following addresses are reserved: (0000 XXXX) and (1111 XXXX), where XXXX can be any bit combinations. This implies that in a 7-bit I2C address system, there are 112 potential device addresses, hence the number of devices that can be supported.

Data Transmission

In idle state, SCL and SDA buses are high. Transmission is initiated by master who puts a clock signal on SCL and generates a start condition(s) on SDA. The Master puts an address on the bus and states whether this is a read access or write access. After R/W bit, slave sends an ACK to indicate if it recognized the address.


Communication via I2C is more complex than with a UART or SPI solution. The signaling must adhere to a certain protocol for the devices on the bus to recognize it as valid I2C communication. Fortunately, most devices take care of all the fiddly details for you, allowing you to concentrate on the data you wish to exchange.



Messages are broken up into two types of frame: an address frame, where the master indicates the slave to which the message is being sent, and one or more data frames, which are 8-bit data messages passed from master to slave or vice versa. Data is placed on the SDA line after SCL goes low, and is sampled after the SCL line goes high. The time between clock edge and data read/write is defined by the devices on the bus and will vary from chip to chip.

Start Condition

To initiate the address frame, the master device leaves SCL high and pulls SDA low. This puts all slave devices on notice that a transmission is about to start. If two master devices wish to take ownership of the bus at one time, whichever device pulls SDA low first wins the race and gains control of the bus. It is possible to issue repeated starts, initiating a new communication sequence without relinquishing control of the bus to other masters; we'll talk about that later.

Address Frames

The address frame is always first in any new communication sequence. For a 7-bit address, the address is clocked out most significant bit (MSB) first, followed by a R/W bit indicating whether this is a read (1) or write (0) operation.

The 9th bit of the frame is the NACK/ACK bit. This is the case for all frames (data or address). Once the first 8 bits of the frame are sent, the receiving device is given control over SDA. If the receiving device does not pull the SDA line low before the 9th clock pulse, it can be inferred that the receiving device either did not receive the data or did not know how to parse the message. In that case, the exchange halts, and it's up to the master of the system to decide how to proceed.

Data Frames

After the address frame has been sent, data can begin being transmitted. The master will simply continue generating clock pulses at a regular interval, and the data will be placed on SDA by either the master or the slave, depending on whether the R/W bit indicated a read or write operation. The number of data frames is arbitrary, and most slave devices will auto-increment the internal register, meaning that subsequent reads or writes will come from the next register in line.

Stop condition

Once all the data frames have been sent, the master will generate a stop condition. Stop conditions are defined by a 0->1 (low to high) transition on SDA after a 0->1 transition on SCL, with SCL remaining high. During normal data writing operation, the value on SDA should not change when SCL is high, to avoid false stop conditions.

Sometimes, it is important that a master device be allowed to exchange several messages in one go, without allowing other master devices on the bus to interfere. For this reason, the repeated start condition has been defined.

To perform a repeated start, SDA is allowed to go high while SCL is low, SCL is allowed to go high, and then SDA is brought low again while SCL is high. Because there was no stop condition on the bus, the previous communication wasn't truly completed and the current master maintains control of the bus.

At this point, the next message can begin transmission. The syntax of this new message is the same as any other message--an address frame followed by data frames. Any number of repeated starts is allowed, and the master will maintain control of the bus until it issues a stop condition.

These are but a few protocols that are used at the physical level in communication amongst IoT devices. At other levels, other protocols are employed. There are wireless means of communicating too. We will look at those as they become necessary. Next, we’ll start a basic project that will help us to put what we’ve learnt so far into use.

Rene Novor X.K
Mor-Lan Technologies.


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